C8051F045-GQ Silicon Laboratories Inc, C8051F045-GQ Datasheet - Page 262
![IC 8051 MCU 64K FLASH 64TQFP](/photos/12/18/121883/c8051f045-gq_sml.jpg)
C8051F045-GQ
Manufacturer Part Number
C8051F045-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1210
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C8051F040/1/2/3/4/5/6/7
262
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3-2: NSSMD1-NSSMD0: Slave Select Mode.
Bit 1:
Bit 0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to
the SPI0 data register was attempted while a data transfer was in progress. It must be
cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive
buffer still holds unread data from a previous transfer and the last bit of the current transfer
is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It
must be cleared by software.
Selects between the following NSS operation modes:
(See
Slave Mode Operation” on page
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
Bit6
Section “20.2. SPI0 Master Mode Operation” on page 257
SFR Definition 20.2. SPI0CN: SPI0 Control
MODF
R/W
Bit5
RXOVRN NSSMD1 NSSMD0
R/W
Bit4
259).
Rev. 1.5
R/W
Bit3
R/W
Bit2
TXBMT
Bit1
R
and
SFR Address:
Section “20.3. SPI0
SPIEN
SFR Page:
R/W
Bit0
0xF8
0
Addressable
Reset Value
00000110
Bit
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