C8051F346-GQ Silicon Laboratories Inc, C8051F346-GQ Datasheet - Page 116
![IC 8051 MCU FLASH 64K 32LQFP](/photos/12/18/121867/c8051f346-gq_sml.jpg)
C8051F346-GQ
Manufacturer Part Number
C8051F346-GQ
Description
IC 8051 MCU FLASH 64K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets
1.C8051F349-GQ.pdf
(276 pages)
2.C8051F346-GQ.pdf
(1 pages)
3.C8051F347-GQ.pdf
(296 pages)
Specifications of C8051F346-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
5.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
25
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1304
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F346-GQ
Manufacturer:
SiliconL
Quantity:
578
Company:
Part Number:
C8051F346-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F346-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13.3. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 13.2.
13.4. Port Configuration
The External Memory Interface appears on Ports 4, 3, 2, and 1 when it is used for off-chip memory access.
When the EMIF is used, the Crossbar should be configured to skip over the control lines P1.7 (WR), P1.6
(RD), and if multiplexed mode is selected P1.3 (ALE) using the P1SKIP register. For more information
about configuring the Crossbar, see
through Port 3)” on page
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See
Output” on page 142
Port latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dor-
mant state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
116
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
5. Set up timing to interface with off-chip memory or peripherals.
(push-pull is most common), and skip the associated pins in the crossbar.
logic ‘1’).
select, or off-chip only).
for more information about the Crossbar and Port operation and configuration. The
142.
Section “Figure 15.1. Port I/O Functional Block Diagram (Port 0
Rev. 1.3
Section “15. Port Input/