MCF51CN128CLH Freescale Semiconductor, MCF51CN128CLH Datasheet - Page 22

IC MCU 32BIT 128K FLASH 64-LQFP

MCF51CN128CLH

Manufacturer Part Number
MCF51CN128CLH
Description
IC MCU 32BIT 128K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51CNr
Datasheets

Specifications of MCF51CN128CLH

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, SCI, SPI
Peripherals
LVD, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF51CN
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
24 KB
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
54
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 12 Channel
Package
64LQFP
Device Core
ColdFire
Family Name
MCF51CN
Maximum Speed
50.33 MHz
Number Of Timers
2
For Use With
TWR-MCF51CN - KIT TOWER BOARDTWR-MCF51CN-KIT - KIT TOWER BOARD/SERIAL/ELEVATOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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1
2
3
4
5
6
Electrical Characteristics
22
Num C
10
11
12
13
14
15
16
17
18
19
8
9
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is
already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
given interval.
Below D
MCG is already in lock, then the MCG may stay in lock.
Below D
Table 11. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125 °C Ambient)
C
C
C FLL acquisition time
D PLL acquisition time
C
D VCO operating frequency
D Lock entry frequency tolerance
D Lock exit frequency tolerance
D Lock time - FLL
D Lock time - PLL
D
P
Resolution of trimmed DCO output
frequency at fixed voltage and
temperature (not using FTRIM)
Total deviation of trimmed DCO output
frequency over voltage and
temperature
Total deviation of trimmed DCO output
frequency over fixed voltage and
temperature range of 0 - 70
Long term Jitter of DCO output clock
(averaged over 2ms interval)
Loss of external clock minimum
frequency - RANGE = 0
lock
unl
minimum, the MCG does not exit lock if already in lock. Above D
minimum, the MCG is guaranteed to enter lock. Above D
Rating
2
3
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
DD
°C
and V
4
6
5
SS
and variation in crystal oscillator frequency increase the C
Δf
t
t
Symbol
pll_acquire
fll_acquire
f
Δf
Δf
t
t
dco_res_t
C
pll_lock
loc_low
D
fll_lock
D
f
dco_t
dco_t
Jitter
vco
lock
unl
lock
maximum, the MCG does not enter lock. But if the
(3/5) x f
± 1.49
± 4.47
unl
Min
7.0
maximum, the MCG is guaranteed to exit lock.
int
Typical
+ 0.5
± 0.2
± 0.5
0.02
-1.0
Freescale Semiconductor
1075(1/
t
1075(1/
t
pll_acquire+
fll_acquire+
± 2.98
± 5.97
± 0.4
Max
55.0
± 2
± 1
0.2
Jitter
ef)
1
1
)
f
f
int_t
pll_r
percentage for a
BUS
%f
%f
%f
%f
MHz
Unit
kHz
ms
ms
%
%
.
s
s
dco
dco
dco
dco

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