MCF51CN128CLH Freescale Semiconductor, MCF51CN128CLH Datasheet - Page 2

IC MCU 32BIT 128K FLASH 64-LQFP

MCF51CN128CLH

Manufacturer Part Number
MCF51CN128CLH
Description
IC MCU 32BIT 128K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51CNr
Datasheets

Specifications of MCF51CN128CLH

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, SCI, SPI
Peripherals
LVD, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF51CN
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
24 KB
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
54
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 12 Channel
Package
64LQFP
Device Core
ColdFire
Family Name
MCF51CN
Maximum Speed
50.33 MHz
Number Of Timers
2
For Use With
TWR-MCF51CN - KIT TOWER BOARDTWR-MCF51CN-KIT - KIT TOWER BOARD/SERIAL/ELEVATOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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• System Protection
• Development Support
• Peripherals
• Input/Output
2
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer with programmable start/stop conditions
– ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address;
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base,
– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler
– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions
– 16 keyboard interrupt (KBI) pins with selectable polarity
– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on
– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)
includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and
voltage. PLL derives a higher accuracy clock source derived by an external reference
clock
9S12x families debug modules
sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
mode; MSB-first or LSB-first shifting
interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
center-aligned PWM on each channel
time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
all output pins
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor

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