R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 14

• Manufacturer Part Number: R5F21134DFP#U0
• Description: IC R8C MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/13r

Specifications of R5F21134DFP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 22
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1024Byte
• Cpu Speed: 20MHz
• No. Of Timers: 16
• Digital Ic Case: RoHS Compliant
• Controller Family/series: R8C/13
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R8C/13 Group
Rev.1.20
REJ03B0069-0120
Table 4.3 SFR Information(3)
X : U n d e f i n e d
N O T E S :
A d d r e s s
1 . B l a n k s p a c e s a r e r e s e r v e d . N o a c c e s s i s a l l o w e d .
2 . W h e n o u t p u t c o m p a r e m o d e ( t h e T C C 1 3 b i t i n t h e T C C 1 r e g i s t e r = 1 ) i s s e l e c t e d, t h e v a l u e a f t e r r e s e t i s s e t t o “ F F F F
0 0 8 0
0 0 8 1
0 0 8 2
0 0 8 3
0 0 8 4
0 0 8 5
0 0 8 6
0 0 8 7
0 0 8 8
0 0 8 9
0 0 8 A
0 0 8 B
0 0 8 C
0 0 8 D
0 0 8 E
0 0 8 F
0 0 9 0
0 0 9 1
0 0 9 2
0 0 9 3
0 0 9 4
0 0 9 5
0 0 9 6
0 0 9 7
0 0 9 8
0 0 9 9
0 0 9 A
0 0 9 B
0 0 9 C
0 0 9 D
0 0 9 E
0 0 9 F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
Jan 27, 2006
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
1 6
1 6
1 6
1 6
16
16
16
16
16
16
16
16
16
16
16
16
T i m e r Y , Z m o d e r e g i s t e r
P r e s c a l e r Y r e g i s t e r
T i m e r Y s e c o n d a r y r e g i s t e r
T i m e r Y p r i m a r y r e g i s t e r
T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r
P r e s c a l e r Z r e g i s t e r
T i m e r Z s e c o n d a r y r e g i s t e r
T i m e r Z p r i m a r y r e g i s t e r
T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r
T i m e r X m o d e r e g i s t e r
P r e s c a l e r X r e g i s t e r
T i m e r X r e g i s t e r
C o u n t s o u r c e s e t r e g i s t e r
T i m e r C r e g i s t e r
External input enable register
K e y i n p u t e n a b l e r e g i s t e r
Timer C control register 0
T i m e r C c o n t r o l r e g i s t e r 1
Capture, compare 0 register
Compare 1 register
UART0 transmit/receive mode register
U A R T 0 b i t r a t e r e g i s t e r
U A R T 0 t r a n s m i t b u f f e r r e g i s t e r
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0
U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
UART0 receive buffer register
U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r
U A R T 1 b i t r a t e r e g i s t e r
U A R T 1 t r a n s m i t b u f f e r r e g i s t e r
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0
U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1
U A R T 1 r e c e i v e b u f f e r r e g i s t e r
U A R T t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2
page 12 of 27
(1)
R e g i s t e r
T Y Z M R
P U M
T Y Z O C
T X M R
INTEN
K I E N
P R E Y
T Y S C
T Y P R
P R E Z
T Z S C
T Z P R
P R E X
T X
T C S S
T C
TCC0
T C C 1
TM0
TM1
U0MR
U 0 B R G
U 0 T B
U 0 C 0
U 0 C 1
U0RB
U 1 M R
U 1 B R G
U 1 T B
U 1 C 0
U 1 C 1
U 1 R B
U C O N
Symbol
4. Special Function Register (SFR)
X X
0 0
F F
F F
F F
0 0
F F
F F
F F
0 0
0 0
F F
F F
0 0
0 0
0 0
00
0 0
00
0 0
00
00
FF
FF
00
X X
X X
X X
0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0
XX
XX
X X
X X
X X
0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0
X X
0 0
0 0
1 6
1 6
1 6
1 6
1 6
1 6
1 6
16
1 6
16
1 6
16
16
16
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
16
16
1 6
1 6
1 6
1 6
1 6
16
16
1 6
1 6
1 6
1 6
A f t e r r e s e t
(2)
1 6
2
2
2
2
”.