R5F21132FP#U0 Renesas Electronics America, R5F21132FP#U0 Datasheet - Page 67

• Manufacturer Part Number: R5F21132FP#U0
• Description: IC R8C MCU FLASH 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/13r

Specifications of R5F21132FP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Table 10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits
• I Flag
• IR Bit
• ILVL2 to ILVL0 Bits and IPL
The following are conditions under which an interrupt is accepted:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
000
001
010
011
100
101
110
111
Jan 27, 2006
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit
is cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority
levels enabled by the IPL.
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
2
2
2
2
2
2
2
2
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
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Interrupt priority
level
Highest
Lowest
Priority
order
Table 10.4 Interrupt Priority Levels Enabled
000
001
010
011
100
101
110
111
IPL
2
2
2
2
2
2
2
2
by IPL
Interrupt levels 1 and above are enabled
All maskable interrupts are disabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
Enabled interrupt priority levels
10.1 Interrupt Overview