C8051F364-GQ Silicon Laboratories Inc, C8051F364-GQ Datasheet - Page 253
C8051F364-GQ
Manufacturer Part Number
C8051F364-GQ
Description
IC 8051 MCU 32K FLASH 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F364-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1646
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Bit 7:
Bit 6:
Bits 5–4: T1M1–T1M0: Timer 1 Mode Select.
Bit 3:
Bit 2:
Bits 1–0: T0M1–T0M0: Timer 0 Mode Select.
SFR Page:
SFR Address:
GATE1
R/W
Bit7
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis-
ter IT01CF (see SFR Definition 10.7).
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
These bits select the Timer 1 operation mode.
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in regis-
ter IT01CF (see SFR Definition 10.7).
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
These bits select the Timer 0 operation mode.
all pages
0x89
T1M1
T0M1
C/T1
0
0
1
1
0
0
1
1
R/W
Bit6
T1M0
T0M0
0
1
0
1
0
1
0
1
SFR Definition 21.2. TMOD: Timer Mode
T1M1
R/W
Bit5
Mode 2: 8-bit counter/timer with auto-reload
Mode 2: 8-bit counter/timer with auto-reload
T1M0
Mode 3: Two 8-bit counter/timers
R/W
Bit4
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 3: Timer 1 inactive
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
GATE0
R/W
Bit3
Mode
Mode
C/T0
R/W
Bit2
T0M1
R/W
Bit1
T0M0
R/W
Bit0
00000000
Reset Value
253
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