C8051F412-GQ Silicon Laboratories Inc, C8051F412-GQ Datasheet - Page 200
C8051F412-GQ
Manufacturer Part Number
C8051F412-GQ
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F41xr
Specifications of C8051F412-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 20x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Dac
2-ch x 12-bit
No. Of I/o's
24
Ram Memory Size
2368Byte
Cpu Speed
50MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
32LQFP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1453 - ADAPTER PROGRAM TOOLSTICK F410336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1310
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F412-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F412-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F410/1/2/3
200
ARBLOST
TXMODE
MASTER
ACKRQ
STO
ACK
STA
Bit
SI
• A START is generated.
• START is generated.
• SMB0DAT is written before the start of an
• A START followed by an address byte is
• A STOP is detected while addressed as a
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
• A repeated START is detected as a MASTER
• SCL is sensed low while attempting to gener-
• SDA is sensed low while transmitting a ‘1’
• The incoming ACK value is low (ACKNOWL-
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
• A byte has been received.
• A START or repeated START followed by a
• A STOP has been received.
Table 21.3. Sources for Hardware Changes to SMB0CN
SMBus frame.
received.
slave.
response value is needed.
when STA is low (unwanted repeated START).
ate a STOP or repeated START condition.
(excluding ACK bits).
EDGE).
ACK/NACK received.
slave address + R/W has been received.
Set by Hardware When:
Rev. 1.1
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
• Must be cleared by software.
• A pending STOP is generated.
• If STO is set by hardware, it must be
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
• Must be cleared by software.
start of an SMBus frame.
cleared by software.
ACKNOWLEDGE).
Cleared by Hardware When:
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