MC9S08AW60MFGE Freescale Semiconductor, MC9S08AW60MFGE Datasheet - Page 75

• Manufacturer Part Number: MC9S08AW60MFGE
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW60MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• For Use With: DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9.5
This register is used to control the MCLK clock output.
5.9.6
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
Freescale Semiconductor
Reserved
Reset
Reset
MCSEL
ID[11:8]
Field
Field
MPE
2:0
7:4
3:0
4
W
W
R
R
System MCLK Control Register (SMCLK)
System Device Identification Register (SDIDH, SDIDL)
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08AC16 Series is hard coded to the value 0x012. See also ID bits in
—
0
0
7
7
Figure 5-7. System Device Identification Register — High (SDIDH)
= Unimplemented or Reserved
= Unimplemented or Reserved
—
0
0
6
6
Figure 5-6. System MCLK Control Register (SMCLK)
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Table 5-7. SMCLK Register Field Descriptions
Table 5-8. SDIDH Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
—
0
0
5
5
Equation
MPE
—
0
4
4
5-1.
Description
Description
ID11
Chapter 5 Resets, Interrupts, and System Configuration
3
0
0
3
0
ID10
0
0
2
2
Table
5-9.
MCSEL
ID9
0
0
1
1
Eqn. 5-1
ID8
0
0
0
0
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