MC9S08AW60MFGE Freescale Semiconductor, MC9S08AW60MFGE Datasheet - Page 101

• Manufacturer Part Number: MC9S08AW60MFGE
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW60MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• For Use With: DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
PTEDS[7:0]
PTESE[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTESE7
PTEDS7
Output Slew Rate Control Enable for Port E Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high
output drive for the associated PTE pin.
0 Low output drive enabled for port E bit n.
1 High output drive enabled for port E bit n.
0
0
7
7
Figure 6-33. Output Slew Rate Control Enable for Port E (PTESE)
Figure 6-34. Output Drive Strength Selection for Port E (PTEDS)
PTESE6
PTEDS6
0
0
6
6
Table 6-24. PTESE Register Field Descriptions
Table 6-25. PTEDS Register Field Descriptions
PTESE5
PTEDS5
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
5
PTESE4
PTEDS4
0
0
4
4
Description
Description
PTEDS3
PTESE3
3
0
3
0
PTEDS2
PTESE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTESE1
PTEDS1
0
0
1
1
PTESE0
PTEDS0
0
0
0
0
101