C8051F706-GQ Silicon Laboratories Inc, C8051F706-GQ Datasheet - Page 151
![IC 8051 MCU 16K FLASH 48-TQFP](/photos/12/17/121753/c8051f706-gq_sml.jpg)
C8051F706-GQ
Manufacturer Part Number
C8051F706-GQ
Description
IC 8051 MCU 16K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F706-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4 x 16 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1636
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F706-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F706-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
22.4.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code
Note: On C8051F70x/71x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
22.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
9. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
10.Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
this rise time specification, then add an external VDD brownout circuit to the /RST pin of the device that
holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts /RST
if VDD drops below the minimum device operating voltage.
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web site.
source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase Flash pages.
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web site.
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
called with an illegal address does not result in modification of the Flash.
or erase Flash without generating a Flash Error Device Reset.
On C8051F70x/71x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
Rev. 1.0
C8051F70x/71x
151
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