C8051F705-GQ Silicon Laboratories Inc, C8051F705-GQ Datasheet - Page 165
![IC 8051 MCU 15K FLASH 48-TQFP](/photos/12/17/121724/c8051f705-gq_sml.jpg)
C8051F705-GQ
Manufacturer Part Number
C8051F705-GQ
Description
IC 8051 MCU 15K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F705-GQ
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
15KB (15K x 8)
Program Memory Type
FLASH
Eeprom Size
32 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1613
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F705-GQ
Manufacturer:
TI/NSC
Quantity:
210
Company:
Part Number:
C8051F705-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F705-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 165 of 306
- Download datasheet (2Mb)
C8051F70x/71x
25.2. Power-Fail Reset / V
Monitor
DD
When a power-down transition or power irregularity causes V
to drop below V
, the power supply
DD
RST
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 25.2). When V
returns
DD
to a level above V
, the CIP-51 will be released from the reset state. Even though internal data memory
RST
contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level
DD
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is
DD
enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source.
For example, if the V
monitor is disabled by code and a software reset is performed, the V
monitor will
DD
DD
still be disabled after the reset.
Important Note: If the V
monitor is being turned on from a disabled state, it should be enabled before it
DD
is selected as a reset source. Selecting the V
monitor as a reset source before it is enabled and stabi-
DD
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
monitor and configuring it as a reset source from a disabled
DD
state is shown below:
1. Enable the V
monitor (VDMEN bit in VDM0CN = 1).
DD
2. If necessary, wait for the V
monitor to stabilize.
DD
3. Select the V
monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
See Figure 25.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
DD
DD
monitor reset. See Section “9. Electrical Characteristics” on page 47 for complete electrical characteristics
of the V
monitor.
DD
Rev. 1.0
165
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