C8051F505-IQ Silicon Laboratories Inc, C8051F505-IQ Datasheet - Page 63

• Manufacturer Part Number: C8051F505-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F505-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1520

SFR Definition 6.4. ADC0CF: ADC0 Configuration
SFR Address = 0xBC; SFR Page = 0x00
Name
Reset
Bit
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
2:1
Type
0
Bit
A0RPT[1:0] ADC0 Repeat Count
GAINEN
Name
7
1
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4 – 0. SAR Conversion clock
requirements are given in the ADC specification table
BURSTEN = 0: FCLK is the current system clock
BURSTEN = 1: FLCLK is a maximum of 30 Mhz, independent of the current system
clock..
Note: Round up the result of the calculation for AD0SC
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A con-
vert start is required for each conversion unless Burst Mode is enabled. In Burst
Mode, a single convert start can initiate multiple self-timed conversions. Results in
both modes are accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are
set to a value other than '00', the AD0LJST bit in the ADC0CN register must be
set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Gain Enable Bit.
Controls the gain programming. Refer to Section “6.3. Selectable Gain” on page 58
for information about using this bit.
AD0SC
6
1
=
AD0SC[4:0]
-------------------- 1
CLK
R/W
FCLK
5
1
SAR
–
Rev. 1.2
4
1
Function
3
1
C8051F50x/F51x
R/W
2
AD0RPT[1:0]
0
R/W
1
0
GAINEN
R/W
0
0
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