C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 165

• Manufacturer Part Number: C8051F321-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel / 10 bit, 7 Channel
• Package: 28MLP
• Device Core: 8051
• Family Name: C8051F321
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F320/1
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While
SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen-
erates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The
STSTL bit must be reset to ‘0’ by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buff-
ering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time.
In this case, hardware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets
OPRDY to ‘0’. A second interrupt will be generated in this case.
15.13.2.Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode.
Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB
frame; the location of the data packet within each frame may vary, however. Because of this, it is recom-
mended that double buffering be enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be gen-
erated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.
Rev. 1.4
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