C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 157

• Manufacturer Part Number: C8051F321-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel / 10 bit, 7 Channel
• Package: 28MLP
• Device Core: 8051
• Family Name: C8051F321
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor
when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the
processor when a complete data packet has been received; appropriate handshaking signals are automat-
ically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete
data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.
15.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (Figure 15.17). The INDEX register must be
loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
-
USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable
1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The
2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted
3. An IN transaction is completed (this interrupt generated during the status stage of the transac-
4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol
5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware
OPRDY bit (E0CSR.0) is set to ‘1’ by hardware.
to the host; INPRDY is reset to ‘0’ by hardware.
tion).
violation.
sets the DATAEND bit (E0CSR.3).
SOFE: Start of Frame Interrupt Enable
0: SOF interrupt disabled.
1: SOF interrupt enabled.
RSTINTE: Reset Interrupt Enable
0: Reset interrupt disabled.
1: Reset interrupt enabled.
RSUINTE: Resume Interrupt Enable
0: Resume interrupt disabled.
1: Resume interrupt enabled.
SUSINTE: Suspend Interrupt Enable
0: Suspend interrupt disabled.
1: Suspend interrupt enabled.
R/W
Bit6
-
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.4
SOFE
R/W
Bit3
RSTINTE RSUINTE SUSINTE 00000110
R/W
Bit2
R/W
Bit1
C8051F320/1
R/W
Bit0
USB Address:
Reset Value
0x0B
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