MC9S08GT60ACFDER Freescale Semiconductor, MC9S08GT60ACFDER Datasheet - Page 98
![IC MCU 60K FLASH 4K RAM 48-QFN](/photos/12/16/121676/mc9s08gt60acfber_sml.jpg)
MC9S08GT60ACFDER
Manufacturer Part Number
MC9S08GT60ACFDER
Description
IC MCU 60K FLASH 4K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT60ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
MC9S08GT60ACFDERTR
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Chapter 6 Parallel Input/Output
98
PTEDD[7:0]
PTEPE[7:0]
PTESE[7:0]
Reset
Reset
Reset
Field
Field
Field
7:0
7:0
7:0
W
W
W
R
R
R
PTEPE7
PTESE7
PTEDD7
Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Slew Rate Control Enable for Port E Bits — For port E pins that are outputs, these read/write control bits
0 Slew rate control disabled.
1 Slew rate control enabled.
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
0
0
0
7
7
7
determine whether the slew rate controlled outputs are enabled. For port E pins that are configured as inputs,
these bits are ignored.
PTED reads.
PTEDD6
PTEPE6
PTESE6
Figure 6-27. Slew Rate Control Enable for Port E (PTESE)
0
0
0
6
6
6
Figure 6-28. Data Direction for Port E (PTEDD)
Figure 6-26. Pullup Enable for Port E (PTEPE)
Table 6-18. PTEPE Field Descriptions
Table 6-19. PTESE Field Descriptions
Table 6-20. PTEDD Field Descriptions
PTEDD5
PTEPE5
PTESE5
MC9S08GB60A Data Sheet, Rev. 2
0
0
0
5
5
5
PTEDD4
PTEPE4
PTESE4
0
0
0
4
4
4
Description
Description
Description
PTEDD3
PTEPE3
PTESE3
3
0
3
0
3
0
PTEDD2
PTEPE2
PTESE2
0
0
0
2
2
2
PTEPE1
PTESE1
PTEDD1
Freescale Semiconductor
0
0
0
1
1
1
PTEDD0
PTEPE0
PTESE0
0
0
0
0
0
0
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