C8051F562-IQ Silicon Laboratories Inc, C8051F562-IQ Datasheet - Page 231

IC 8051 MCU 32K FLASH 32-QFP

C8051F562-IQ

Manufacturer Part Number
C8051F562-IQ
Description
IC 8051 MCU 32K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Datasheets

Specifications of C8051F562-IQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1698

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F562-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F562-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Values Read
1110
1100 0 0 0 A master data or address byte
1000 1 0 X A master data byte was
0 0 X A master START was gener-
0 0 1 A master data or address byte
Current SMbus State
ated.
was transmitted; NACK
received.
was transmitted; ACK
received.
received; ACK requested.
Table 22.4. SMBus Status Decoding
Rev. 1.1
Typical Response Options
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
C8051F55x/56x/57x
Values to
Write
0 0 X 1100
1 0 X
0 1 X
0 0 X 1100
0 1 X
1 1 X
1 0 X
0 0 X 1000
0 0 1
0 1 0
1 1 0
1 0 1
1 0 0
0 0 1
0 0 0
1000
1100
1100
1110
1110
1110
1110
1110
231

Related parts for C8051F562-IQ