MC9S08AC16CFDE Freescale Semiconductor, MC9S08AC16CFDE Datasheet - Page 90
![IC MCU 8BIT 16K FLASH 48-QFN](/photos/12/16/121633/mc9s08ac16cfde_sml.jpg)
MC9S08AC16CFDE
Manufacturer Part Number
MC9S08AC16CFDE
Description
IC MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC8CFGE.pdf
(336 pages)
Specifications of MC9S08AC16CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Chapter 6 Parallel Input/Output
6.7.2
In addition to the I/O control, port A pins are controlled by the registers listed below.
90
Bits 6 through 3 are reserved bits that must always be written to 0.
Bits 6 through 3 are reserved bits that must always be written to 0.
PTADDn
PTAPEn
Reset
Reset
7, 2:0
7, 2:0
Field
Field
W
W
R
R
PTADD7
PTAPE7
Port A Pin Control Registers (PTAPE, PTASE, PTADS)
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
0
0
7
7
Figure 6-11. Data Direction for Port A Register (PTADD)
Figure 6-12. Internal Pullup Enable for Port A (PTAPE)
R
R
0
0
6
6
Table 6-2. PTADD Register Field Descriptions
Table 6-3. PTAPE Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
R
R
3
0
3
0
PTADD2
PTAPE2
0
0
2
2
1
1
PTADD1
PTAPE1
Freescale Semiconductor
0
0
1
1
PTADD0
PTAPE0
0
0
0
0
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