C8051F337-GM Silicon Laboratories Inc, C8051F337-GM Datasheet - Page 167

• Manufacturer Part Number: C8051F337-GM
• Description: IC MCU 16K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F337-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1451 - ADAPTER PROGRAM TOOLSTICK F330
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1428-5

23. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
Figure 23.1. SPI Block Diagram
7
6
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
SPI0CFG
Control
SPI0DAT
1
SPI0DAT
Read
0
Rev.1.0
Tx Data
Rx Data
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
C8051F336/7/8/9
C
R
O
S
S
B
A
R
SPI IRQ
Port I/O
167