MC9S08GT8ACFCE Freescale Semiconductor, MC9S08GT8ACFCE Datasheet - Page 174
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MC9S08GT8ACFCE
Manufacturer Part Number
MC9S08GT8ACFCE
Description
IC MCU 8K FLASH 1K RAM 32-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT8ACFBER.pdf
(300 pages)
Specifications of MC9S08GT8ACFCE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Serial Communications Interface (S08SCIV1)
11.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
174
SBR[12:8]
SBR[7:0]
Reset
Reset
Field
Field
4:0
7:0
W
W
R
R
Register Definition
SBR7
SCI Baud Rate Registers (SCIxBDH, SCIxBHL)
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
0
0
0
7
7
= Unimplemented or Reserved
SBR6
0
0
0
6
6
Table 11-1. SCIxBDH Register Field Descriptions
Table 11-2. SCIxBDL Register Field Descriptions
Figure 11-4. SCI Baud Rate Register (SCIxBDH)
Figure 11-5. SCI Baud Rate Register (SCIxBDL)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
SBR5
0
0
0
5
5
Memory
SBR12
SBR4
0
0
4
4
Description
Description
chapter of this data sheet for the absolute address
SBR11
SBR3
3
0
3
0
SBR10
SBR2
0
1
2
2
Freescale Semiconductor
SBR9
SBR1
0
0
1
1
Table
Table
11-2.
11-1.
SBR8
SBR0
0
0
0
0
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