C8051T606-ZM Silicon Laboratories Inc, C8051T606-ZM Datasheet - Page 106
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C8051T606-ZM
Manufacturer Part Number
C8051T606-ZM
Description
IC 8051 MCU 1.5K-EEPROM 10-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Specifications of C8051T606-ZM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
10-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T606DK
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Data Converters
-
For Use With
336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1663-2
C8051T606-ZMR
C8051T606-ZMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T606-ZMR
Manufacturer:
STM
Quantity:
4 037
C8051T600/1/2/3/4/5/6
22. Port Input/Output
Digital and analog resources are available through eight I/O pins on the C8051T600/1/2/3/4/5, or six I/O
pins on the C8051T606. Port pins P0.0-P0.7 can be defined as general-purpose I/O (GPIO), assigned to
one of the internal digital resources, or assigned to an analog function as shown in Figure 22.1. Port pin
P0.7 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which
functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility
is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the P0 port latch, regardless of the crossbar settings.
The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.3 and Figure 22.4). The registers XBR1 and XBR2, defined in SFR Definition 22.2 and SFR
Definition 22.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Section “8. Electrical Characteristics” on page 30.
106
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
PCA
CP0
Figure 22.1. Port I/O Functional Block Diagram
Port Latch
2
2
2
4
2
P0
(P0.0-P0.7)
8
Rev. 1.2
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
(ADC0, CP0, VREF, EXTCLK)
To Analog Peripherals
8
P0MDIN Registers
P0MDOUT,
Cells
I/O
P0
P0.0
(‘T600/1/2/3/4/5 Only)
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
(‘T600/1/2/3/4/5 Only)
P0.7