EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 318

• Manufacturer Part Number: EZ80F91NAA50EG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4565

Table 189. EMAC_IPGT Back-to-Back Settings for Full- and Half-Duplex Modes
PS027001-0707
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
Duplex
*12h
Half
Clock Period = 40 ns
MII, RMII/SMII, PMD
(100 Mbps)
Duplex
IPGT[6:0]
0Dh
0Ch
0Bh
10h
15h
20h
Full
The equations for back-to-back Transmit IPG are determined by the following:
Table 190
FULL-DUPLEX Mode (3 clocks + IPGT clocks) * clock period = IPG
HALF-DUPLEX Mode (6 clocks + IPGT clocks) * clock period = IPG
Interpacket
0.44 µs
0.60 µs
0.76 µs
0.96 µs
1.40 µs
0.12 µs
Gap
on page 311 lists the IPGR2 settings for the non-back-to-back packets.
Duplex
Half
12h
Clock Period = 400 ns
MII, RMII/SMII
(10 Mbps)
Duplex
IPGT[6:0]
0Ch
Full
00h
08h
10h
15h
20h
Interpacket
14.0 µs
1.2 µs
4.4 µs
6.0 µs
7.5 µs
9.6 µs
Gap
Duplex
Half
5Ah
Ethernet Media Access Controller
Clock Period = 100 ns
Product Specification
ENDEC Mode
(10 Mbps)
Duplex
IPGT[6:0]
5Dh
Full
10h
18h
20h
40h
20h
eZ80F91 ASSP
Interpacket
13.0 µs
1.9 µs
2.7 µs
3.5 µs
6.7 µs
9.6 µs
Gap
310