STR911FAW42X6 STMicroelectronics, STR911FAW42X6 Datasheet - Page 15
![MCU 256KB FLASH 96K RAM 128LQFP](/photos/12/15/121557/str911faw42x6_sml.jpg)
STR911FAW42X6
Manufacturer Part Number
STR911FAW42X6
Description
MCU 256KB FLASH 96K RAM 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR911FAW42X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR911x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STR9-COMSTICK, STR910-EVAL, STR91X-SK/HIT, STR91X-SK/IAR, STR91X-SK/KEI, STR91X-SK/RAI, STR9-DK/RAIS, STR91X-DK/IAR, STX-PRO/RAIS, STR912-D/RAIS, STR79-RVDK/CPP, STR79-RVDKCPP/9, STR79-RVDK, STR79-RVDK/9, STR9-RVDK/BAS, STR79-RVDK/UPG
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES497-5067 - BOARD EVAL FOR STR910 FAMILY497-5066 - KIT STARTER KEIL FOR STR910497-5065 - KIT STARTER IAR KICKSTART STR912497-5064 - KIT STARTER FOR STR910 FAMILY497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-6280
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR911FAW42X6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STR911FAW42X6
Manufacturer:
ST
Quantity:
20 000
STR91xFAxxx
3.5
3.5.1
3.5.2
3.6
SRAM (64 Kbytes or 96 Kbytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-
cycle data accesses. As shown in
Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to
allow the DMA unit on the AHB to also access the SRAM.
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was
last to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long
as the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth
with peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this
instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the operating voltage on the main digital supplies (VDD
and VDDQ are lost or sag below the LVD threshold. Automatic switchover to SRAM can be
disabled by firmware if it is desired that the battery will power only the RTC and not the
SRAM during standby.
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 14 request signals to service other peripherals and interfaces (USB, SSP,
ADC, UART, Timers, EMI, and external request pins). Both single word and burst DMA
transfers are supported. Memory-to-memory transfers are supported in addition to memory-
peripheral transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration
is described in
list descriptor tables. Of the 16 DMA request signals, two are assigned to external inputs.
The DMA unit can move data between external devices and resources inside the STR91xFA
through the EMI bus.
Section
3.5.1. Efficient DMA transfers are managed by firmware using linked
Doc ID 13495 Rev 6
Figure
1, the D-TCM shares SRAM access with the
Functional overview
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