EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 325
EZ80F91AZ050EG
Manufacturer Part Number
EZ80F91AZ050EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91AZ050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3867
EZ80F91AZ050EG
EZ80F91AZ050EG
Available stocks
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Manufacturer
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Table 202. EMAC PHY Unit Select Address Register
Table 203. EMAC Transmit Polling Timer Register (EMAC_PTMR = 0040h)
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:5]
[4:0]
FIAD
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_PTMR
EMAC PHY Unit Select Address Register
The EMAC PHY Unit Select Address Register allows the selection of multiple connected
external PHY devices. See
EMAC Transmit Polling Timer Register
This register sets the Transmit Polling Period in increments of TPTMR = SYSCLK ÷ 256.
Whenever this register is written, the status of the Transmit Buffer Descriptor is checked
to determine if the EMAC owns the Transmit buffer. It then rechecks this status every
TPTMR (calculated by TPTMR x EMAC_PTMR[7:0]). The Transmit Polling Timer is
disabled if this register is set to
transmission is in progress when EMAC_PTMR is set to
plete. See
Value
000
00h–1Fh Programmable 5-bit value that selects an external PHY.
Value
00h–FFh The Transmit polling period.
R/W
Table
Description
Reserved.
R
7
0
7
0
Description
203.
R/W
R
6
0
6
0
R/W
Table
R
5
0
5
0
00h
202.
R/W
R/W
4
0
4
0
(which also disables the transmitting of packets). If a
R/W
R/W
3
0
3
0
(EMAC_FIAD = 003Fh)
R/W
R/W
2
0
2
0
00h
R/W
R/W
Ethernet Media Access Controller
1
0
1
0
, the transmission will com-
Product Specification
R/W
R/W
0
0
0
0
316
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