ST72F325AR9T6 STMicroelectronics, ST72F325AR9T6 Datasheet - Page 63
![MCU 8BIT 60KB FLASH/ROM 64-TQFP](/photos/6/76/67655/497-64-tqfp_sml.jpg)
ST72F325AR9T6
Manufacturer Part Number
ST72F325AR9T6
Description
MCU 8BIT 60KB FLASH/ROM 64-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F325K6T6.pdf
(197 pages)
Specifications of ST72F325AR9T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
A/d Bit Size
10 bit
A/d Channels Available
16
Height
1.4 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3.8 V, 4.5 V
Width
10 mm
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5600
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F325AR9T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
- Current page: 63 of 197
- Download datasheet (4Mb)
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Table 16. Main Clock Controller Register Map and Reset Values
Address
002Dh
(Hex.)
002Ch
002Bh
SICSR
Reset Value
MCCSR
Reset Value
MCCBCR
Reset Value
Register
Label
AVDS
MCO
7
0
0
0
AVDIE
CP1
6
0
0
0
AVDF
CP0
5
0
0
0
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
LVDRF
BC1
7
0
SMS
0
0
1
1
4
0
0
x
0
BC0
0
1
0
1
TB1
3
0
0
0
0
Beep mode with f
0
~500-Hz
~1-KHz
~2-KHz
CSSIE
TB0
2
0
0
0
0
Off
CSSD
BC1
OIE
0
~50% duty cycle
1
0
0
0
OSC2
Beep signal
ST72325xx
BC1
Output
=8MHz
WDGRF
BC0
OIF
63/197
0
x
0
0
BC0
0
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