ST72F321BAR9T6 STMicroelectronics, ST72F321BAR9T6 Datasheet - Page 174

• Manufacturer Part Number: ST72F321BAR9T6
• Description: MCU 8BIT 60KB FLASH/ROM 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321BAR9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5583

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
14 ST72321B DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72321B
ST72P321B devices are Factory Advanced Serv-
ice Technique ROM (FASTROM) versions: they
are
14.1 FLASH OPTION BYTES
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC
clock source enabled. In masked ROM devices,
the option bytes are fixed in hardware by the ROM
code (see option list).
OPTION BYTE 0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = Reserved, must be kept at default value.
174/187
Default
factory-programmed
7
1
WDG
devices
1
STATIC OPTION BYTE 0
1
are
1
0
HDFlash
VD
ROM
0
0
1
versions.
devices.
1
1
0
FLASH devices are shipped to customers with a
default content, while ROM/FASTROM factory
coded parts contain the code supplied by the cus-
tomer. This implies that FLASH devices have to be
configured by the customer using the Option Bytes
while the ROM/FASTROM devices are factory-
configured.
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to
12.3.2 on page 141
OPT2 = Reserved, must be kept at default value.
OPT1= PKG0 Package selection bit 0
This option bit is not used.
Lowest Threshold: (V
Med. Threshold (V
Highest Threshold (V
1
17
Selected Low Voltage Detector
1
LVD and AVD Off
OSCTYPE
STATIC OPTION BYTE
1
1
DD
~3.5V)
DD
DD
0
0
~3V)
~4V)
2
1
OSCRANGE
1
1
VD1
1
1
0
0
0
1
section
VD0
1
0
1
0
0
1