EZ80F93AZ020EG Zilog, EZ80F93AZ020EG Datasheet - Page 48
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020EG
Manufacturer Part Number
EZ80F93AZ020EG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3873
EZ80F93AZ020EG
EZ80F93AZ020EG
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PS015313-0508
Note:
GPIO Mode 5—
GPIO Mode 6—
falling edge on the pin cause an interrupt request to be sent to the CPU. Writing a 1 to the
Port x Data register bit position resets the corresponding interrupt request. Writing a 0 pro-
duces no effect. The programmer must set the Port x Data register before entering the
edge-triggered interrupt mode.
GPIO Mode 7—
the alternate (secondary) functions assigned to the pin. For example, the alternate mode
function for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When
GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the alter-
nate function's data output and tristate control, respectively. The value in the Port x Data
register produces no effect on operation.
GPIO Mode 8—
rupt request is generated when the level at the pin is the same as the level stored in the Port
x Data register. The port pin value is sampled by the system clock. The input pin must be
held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source.
GPIO Mode 9—
value in the Port x Data register determines if a positive or negative edge causes an inter-
rupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. The interrupt request remains active until a 1 is writ-
ten to the corresponding interrupt request of the Port x Data register bit. Writing a 0 pro-
duces no effect on operation. The programmer must set the Port x Data register before
entering the edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is displayed in
Input signals are sampled by the system clock before being passed to the alternate
function input.
Reserved. This pin produces high-impedance output.
This bit enables a dual edge-triggered interrupt mode. Both a rising and a
For Ports B, C, and D, the port pin is configured to pass control over to
The port pin is configured for level-sensitive interrupt modes. An inter-
The port pin is configured for single edge-triggered interrupt mode. The
Figure 5
General-Purpose Input/Output
Product Specification
eZ80F92/eZ80F93
on page 42.
41
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