EZ80F93AZ020EG Zilog, EZ80F93AZ020EG Datasheet - Page 192
EZ80F93AZ020EG
Manufacturer Part Number
EZ80F93AZ020EG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3873
EZ80F93AZ020EG
EZ80F93AZ020EG
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PS015313-0508
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during ZDI DEBUG mode.
See
Table 108. ZDI Bus Control Register(ZDI_BUS_STAT = 17h in the ZDI Register Read
Only Address Space)
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F92 device
fetches the data from the memory address currently pointed to by the program counter,
PC; the program counter is then incremented. In Z80
address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory address is
PC[23:0]. Refer to the eZ80
ing Z80
data Read. However, the ZDI register address does not increment automatically when this
register is accessed. As a result, the ZDI master can read any number of data bytes out of
memory through the ZDI Read Memory register. See
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSACK_EN
6
ZDI_BUS_STAT
[5:0]
Table
®
and ADL MEMORY modes. The program counter, PC, increments after each
108.
Value
0
1
0
1
000000
R
®
7
0
CPU User Manual (UM0077) for more information regard-
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
R
5
0
R
4
0
®
Table 109
MEMORY mode, the memory
R
3
0
on page 186.
Product Specification
R
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
R
1
0
R
0
0
185
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