ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 52

• Manufacturer Part Number: ST72F324LJ2T5
• Description: IC MCU 8BIT 8K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324LJ2T5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8242; ST72F324LJ2T5

ST72324Lxx
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Table 16. Main Clock Controller Register Map and Reset Values
52/154
1
Address
002Dh
(Hex.)
002Ch
MCCSR
Reset Value
MCCBCR
Reset Value
Register
Label
MCO
7
0
0
CP1
6
0
0
CP0
5
0
0
MCC BEEP CONTROL REGISTER (MCCBCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
BC1
7
0
SMS
0
0
1
1
4
0
0
0
BC0
0
1
0
1
TB1
3
0
0
0
Beep mode with f
0
~500-Hz
~1-KHz
~2-KHz
TB0
2
0
0
0
Off
BC1
OIE
0
~50% duty cycle
1
0
0
OSC2
Beep signal
BC1
Output
=8MHz
BC0
OIF
0
0
0
BC0
0