ST7FLIT19BF1B6 STMicroelectronics, ST7FLIT19BF1B6 Datasheet - Page 150

• Manufacturer Part Number: ST7FLIT19BF1B6
• Description: IC MCU 8BIT 4K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT19BF1B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit , 13 bit, 7 Channel
• For Use With: 497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5626-5

ST7LITE1xB
OPTION BYTES (Cont’d)
OPTION BYTE 1
OPT7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
OPT6 = PLLOFF PLL disable.
0: PLL enabled
1: PLL disabled (by-passed)
OPT5 = PLL32OFF 32MHz PLL disable.
0: PLL32 enabled
1: PLL32 disabled (by-passed)
OPT4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Notes:
– 1% RC oscillator available on ST7LITE15B and
– If the RC oscillator is selected, then to improve
Table 27. List of valid option combinations
Note 1: Configuration available on ST7LITE15B and ST7LITE19B devices only
Note: see Clock Management Block diagram in
150/159
V
2.7V - 3.3V
3.3V - 5.5V
ST7LITE19B devices only
clock stability and frequency accuracy, it is rec-
ommended to place a decoupling capacitor, typ-
ically 100nF, between the V
close as possible to the ST7 device.
DD
range
Operating conditions
Clock Source
Internal RC 1%
External clock
Internal RC 1%
External clock
1)
1)
DD
and V
SS
pins as
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Figure 14
OPT3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in
Table 26. LVD Threshold Configuration
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Typ f
1MHz @3.3V
4MHz @3.3V
-
0-4MHz
4MHz
-
1MHz @5V
-
8MHz @5V
0-8MHz
-
8 MHz
LVD Off
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
CPU
Configuration
OSC
0
0
1
1
0
0
1
1
-
-
-
-
Option Bits
PLLOFF
Table
1
0
1
0
1
0
1
0
-
-
-
-
26.
LVD1 LVD0
PLLx4x8
1
1
0
0
1
0
1
0
1
1
1
1
-
-
-
-
1
0
1
0