Z8F0213PJ005SC Zilog, Z8F0213PJ005SC Datasheet - Page 67

• Manufacturer Part Number: Z8F0213PJ005SC
• Description: IC ENCORE MCU FLASH 2K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213PJ005SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3461

PS024314-0308
Caution:
Caution:
Caution:
Caution:
Software Interrupt Assertion
Watchdog Timer Interrupt Assertion
Program code generates interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the timeout condi-
tion continues. As it operates on a different (and usually slower) clock domain than the
rest of the device, the Watchdog Timer continues to assert this interrupt for many system
clocks until the counter rolls over.
To avoid missing interrupts, use the following coding style to clear bits in the Interrupt
Request 0 register:
The following coding style used to generate software interrupts by setting bits in the
Interrupt Request registers is not recommended. All incoming interrupts received
between execution of the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to set bits in the Interrupt
Request registers:
To avoid re-triggerings of the Watchdog Timer interrupt after exiting the associated in-
terrupt service routine, it is recommended that the service routine continues to read from
the RSTSTAT register until the
sample:
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt
BTJNZ 5, r0, CLEARWDT ; loop until bit is cleared
Good coding style that avoids lost interrupt requests:
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
bit
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
WDT
bit is cleared as given in the following coding
Z8 Encore! XP
Product Specification
®
Interrupt Controller
F0823 Series
57