Z8F022APB020SG Zilog, Z8F022APB020SG Datasheet - Page 161
Z8F022APB020SG
Manufacturer Part Number
Z8F022APB020SG
Description
IC ENCORE XP MCU FLASH 2K 8DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F08200100KIT.pdf
(264 pages)
Specifications of Z8F022APB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
Z8F022Ax
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
512 KB
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4089
Z8F022APB020SG
Z8F022APB020SG
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Operation
PS022517-0508
Automatic Power-Down
Single-Shot Conversion
Continuous Conversion
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a
conversion is requested using the ADC Control Register.
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a single-
shot conversion:
1. Enable the desired analog inputs by configuring the GPIO pins for alternate function.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
4. When the conversion is complete, the ADC control logic performs the following
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an
analog-to-digital conversion on the selected analog input. Each new data value over-writes
the previous value stored in the ADC Data Registers. An interrupt is generated after each
conversion.
This configuration disables the digital input and output drivers.
The bit fields in the ADC Control Register is written simultaneously:
–
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
operations:
–
–
–
powered-down.
Write to the ANAIN[3:0] field to select one of the 5 analog input sources.
Clear CONT to 0 to select a single-shot conversion.
Write to the VREF bit to enable or disable the internal voltage reference generator.
Set CEN to 1 to start the conversion.
10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
CEN resets to 0 to indicate the conversion is complete.
An interrupt request is sent to the Interrupt Controller.
Z8 Encore! XP
Product Specification
Analog-to-Digital Converter
®
F0822 Series
148
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