Z8F022APB020SG Zilog, Z8F022APB020SG Datasheet - Page 117
Z8F022APB020SG
Manufacturer Part Number
Z8F022APB020SG
Description
IC ENCORE XP MCU FLASH 2K 8DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F08200100KIT.pdf
(264 pages)
Specifications of Z8F022APB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
Z8F022Ax
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
512 KB
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4089
Z8F022APB020SG
Z8F022APB020SG
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Table 57. UART Control 1 Register (U0CTL1)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
MPMD[1]
7
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission by forcing the Transmit data output to 0.
Sending a break interrupts any transmission in progress, so ensure that the transmitter has
finished sending data before setting this bit. The UART does not automatically generate a
STOP Bit when SBRK is deasserted. Software must time the duration of the Break and the
duration of any STOP Bit time desired following the Break.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—STOP Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
MPMD[1:0]—Multiprocessor Mode
If Multiprocessor (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches
11 = The UART generates an interrupt request on all received data bytes for which
MPEN—Multiprocessor (9-bit) Enable
This bit is used to enable Multiprocessor (9-bit) mode.
0 = Disable Multiprocessor (9-bit) mode.
1 = Enable Multiprocessor (9-bit) mode.
the value stored in the Address Compare Register and on all successive data
bytes until an address mismatch occurs.
the most recent address byte matched the value in the Address Compare Register.
MPEN
6
MPMD[0]
5
MPBT
4
F43H
R/W
0
DEPOL
3
Universal Asynchronous Receiver/Transmitter
BRGCTL
Z8 Encore! XP
2
Product Specification
RDAIRQ
1
®
F0822 Series
IREN
0
104
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