LPC2377FBD144,551 NXP Semiconductors, LPC2377FBD144,551 Datasheet - Page 20

• Manufacturer Part Number: LPC2377FBD144,551
• Description: IC ARM7 MCU FLASH 512K 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2377FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 58K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: LPC23
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 58 KB
• Interface Type: CAN, I2S, ISP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 144LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCDMCB2370UME - BOARD EVAL MCB2370 + ULINK-MEMCB2370U - BOARD EVAL MCB2370 + ULINK2MCB2370 - BOARD EVAL NXP LPC2368/2378568-3999 - BOARD EVAL FOR LPC23 ARM MCU622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4411; 935286019551; LPC2377FBD144-S

NXP Semiconductors
LPC2377_78
Product data sheet
7.7.1 Features
7.8.1 Features
7.8 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2377/78
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
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Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode
Low transaction latency
Read and write buffers to reduce latency and to improve performance
8 data and 16 address lines wide static memory support
Two chip selects for static memory devices
Static memory features include:
– Asynchronous page mode read
– Programmable Wait States (WST)
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the
SD/MMC, two SSP, and I
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 June 2010
2
S-bus interfaces.
Single-chip 16-bit/32-bit microcontrollers
LPC2377/78
© NXP B.V. 2010. All rights reserved.
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