LPC2142FBD64,151 NXP Semiconductors, LPC2142FBD64,151 Datasheet - Page 18
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LPC2142FBD64,151
Manufacturer Part Number
LPC2142FBD64,151
Description
IC ARM7 MCU FLASH 64K 64LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2141FBD64151.pdf
(40 pages)
Specifications of LPC2142FBD64,151
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
45
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
16 KB
Interface Type
SCI/UART/SPI/SSP/I2C/USB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
45
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Cpu Family
LPC2000
Device Core
ARM7TDMI-S
Device Core Size
16/32Bit
Frequency (max)
60MHz
Total Internal Ram Size
16KB
# I/os (max)
45
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2140UME - BOARD EVAL MCB2140 + ULINK-MEMCB2140U - BOARD EVAL MCB2140 + ULINK2MCB2140 - BOARD EVAL NXP LPC214X ARM FAM622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-2097 - BOARD EVAL FOR LPC214X ARM MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1762
935280017151
LPC2142FBD64-S
935280017151
LPC2142FBD64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2142FBD64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.11.1 Features
6.12.1 Features
6.12 I
6.13 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain two I
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
(Fast I
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C-bus serial I/O controller
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interface signals. This
module also provides full support for hardware flow control (auto-CTS/RTS).
Compliant with standard I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
2
C-bus).
2
C-bus can be used for test and diagnostic purposes.
Rev. 04 — 17 November 2008
2
C-bus interface.
LPC2141/42/44/46/48
2
Single-chip 16-bit/32-bit microcontrollers
C-bus controllers.
2
C-bus is a multi-master bus, it can be
© NXP B.V. 2008. All rights reserved.
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