DSPIC30F6014-30I/PF Microchip Technology, DSPIC30F6014-30I/PF Datasheet - Page 16
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DSPIC30F6014-30I/PF
Manufacturer Part Number
DSPIC30F6014-30I/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6014-20IPF.pdf
(228 pages)
2.DSPIC30F6014-20IPF.pdf
(22 pages)
3.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6014-30I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
3-Wire/AC97/CAN/I2C/I2S/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601430IPF
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dsPIC30F6011/6012/6013/6014
25. Module: I
DS80198J-page 16
When the I
either in single-master or multi-master mode, the
I
address is detected or not. Therefore, an I
receiver overflow condition occurs and this
condition is indicated by the I2COV flag in the
I2CSTAT register.
This overflow condition inhibits the ability to set the
I
valid data byte is received. Therefore, the I
slave Interrupt Service Routine (ISR) is not called
and the I
receiving the next data byte.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
For applications in which the I
is not required, the following procedure can be
used to receive valid data bytes:
1. Wait until the RBF flag is set.
2. Poll the I
3. If SI2CF is not set in the corresponding
4. If the SI2CF is set in the corresponding
5. Read the I2CRCV buffer to recover valid data
6. Clear the I
7. Go back to step 1 to continue receiving
2
2
C receiver buffer is filled whether a valid slave
C receive interrupt flag (SI2CF) when the last
Interrupt Flag Status (IFSx) register, a valid
address or data byte has not been received for
the current slave. Execute a dummy read of
the I
the RBF flag. Go back to step 1 until SI2CF is
set and then continue to Step 4.
Interrupt Flag Status (IFSx) register, valid data
has been received. Check the D_A flag to
verify that an address or a data byte has been
received.
bytes. This will also clear the RBF flag.
incoming data bytes.
2
C receiver buffer, I2CRCV; this will clear
2
2
C receiver buffer is not read prior
2
2
C
C module is configured as a slave,
C receiver interrupt SI2CIF flag.
2
C receiver interrupt flag SI2CF.
2
C receiver interrupt
2
2
C
C
Work around 2:
Use this work around for applications in which the
I
the RBF and the I2COV flags in the I2CSTAT
register are set due to previous data transfers in
the I
slaves); the following procedure can be used to
receive valid data bytes:
1. When a valid slave address byte is detected,
2. Check the status of the D_A flag and the
3. If the D_A flag is cleared and the I2COV flag
4. Clear the I2COV flag and perform a dummy
5. Verify that the recovered address byte
6. If the D_A flag and the I2COV flag are both set,
2
C receiver interrupt is required. Assuming that
SI2CF bit is set and the I
service routine is called; however, the RBF and
I2COV bits are already set due to data
transfers between other I
I2COV flag in the I2CSTAT register when
executing the I
are set, an invalid data byte was received but a
valid address byte was received. The overflow
condition occurred because the I
buffer was overflowing with previous I
transfers between other I
condition only occurs after a valid slave
address was detected.
read of the I
clear the RBF bit and recover the valid address
byte. This action will also avoid the loss of the
next data byte due to an overflow condition.
matches the current slave address byte. If they
match, the next data to be received is a valid
data byte.
a valid data byte was received and a previous
valid data byte was lost. It will be necessary to
code for handling this overflow condition.
2
C bus (i.e., between master and other
2
2
C receiver buffer, I2CRCV, to
C slave service routine.
© 2008 Microchip Technology Inc.
2
C nodes.
2
C slave interrupt
2
C nodes. This
2
C receive
2
C data