DSPIC30F6010A-30I/PF Microchip Technology, DSPIC30F6010A-30I/PF Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F6010A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 4.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F Family Reference Manual
35.3.2.1.1 External Clocking in Master Mode
DS70272B-page 35-10
To set up the SPI1 module for the Master mode of operation, perform the following steps:
1.
2.
3.
4.
5.
Example 35-1 shows a code snippet for configuring the SPI register for the Master mode.
Example 35-1:
In Master mode, the module can also be configured to operate with an external data clock. SPI1
clock operation is controlled by the DISSCK bit (SPI1CON1<12>). When this bit is set, the
internal data clock is disabled and data is transferred when external clock pulses are presented
on the SCK1 pin. All other aspects of Master mode operation are the same as described above.
/* Following code snippet shows SPI register configuration for MASTER mode*/
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 0;
SPI1CON1bits.DISSCK = 0;
SPI1CON1bits.DISSDO = 0;
SPI1CON1bits.MODE16 = 1;
SPI1CON1bits.SMP = 0;
SPI1CON1bits.CKE = 0;
SPI1CON1bits.CKP = 0;
SPI1CON1bits.MSTEN = 1;
SPI1STATbits.SPIEN = 1;
SPI1BUF = 0x0000;
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 1;
Note:
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 register with MSTEN (SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Enable SPI1 module operation by setting the SPIEN bit (SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF register. Transmission (and reception) will
start as soon as data is written to the SPI1BUF register.
Clear the SPI1IF bit in the IFS0 register.
Set the SPI1IE bit in the IEC0 register.
Write the SPI1IP bits in the IPC2 register to set the interrupt priority.
The DISSCK bit is available only in SPI Master modes.
SPI Configuration – Master Mode
//Clear the Interrupt Flag
//disable the Interrupt
//SPI1CON1 Register Settings
//Internal Serial Clock is Enabled.
//SDO1 pin is controlled by the module.
//Communication is word-wide (16 bits).
//Input Data is sampled at the middle of data
//output time.
//Serial output data changes on transition from
//Idle clock state to active clock state
//Idle state for clock is a low level; active
//state is a high level
//Master Mode Enabled
//Enable SPI Module
//Write data to be transmitted
//Interrupt Controller Settings
//Clear the Interrupt Flag
//Enable the Interrupt
© 2008 Microchip Technology Inc.