DSPIC30F6010A-30I/PF Microchip Technology, DSPIC30F6010A-30I/PF Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F6010A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 4.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
CAN
ADC
QEI
QEI
I
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Accumulation
Accumulation
Consumption
Bus Collision
RX Filters 3,
Timer Gated
Timer Gated
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
4 and 5
Current
Mode
Mode
Mode
Number
Item
18.
19.
20.
21.
22.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
CAN Receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time quanta.
When Timer Gated Accumulation is enabled, the QEI does not
generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
If the ADC module is in an enabled state when the device enters
Sleep Mode, the power-down current (I
exceed the device data sheet specifications.
2
C module is enabled, the dsPIC
Issue Summary
dsPIC30F6010A/6015
PD
) of the device may
®
DSC device
DS80458C-page 3
Revisions
A2 A3 A4
X
X
X
X
X
Affected
X
X
X
X
X
(1)
X
X
X
X
X