PIC17C44-16/L Microchip Technology, PIC17C44-16/L Datasheet - Page 40
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PIC17C44-16/L
Manufacturer Part Number
PIC17C44-16/L
Description
IC MCU OTP 8KX16 PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C44-16L.pdf
(4 pages)
Specifications of PIC17C44-16/L
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
16MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Controller Family/series
PIC17
No. Of I/o's
33
Ram Memory Size
454Byte
Cpu Speed
16MHz
No. Of Timers
4
No. Of Pwm Channels
2
Embedded Interface Type
USART
Rohs Compliant
Yes
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
454 B
Interface Type
SCI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C44-16/L
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC17C4X
6.4.1
The PIC17C4X has four registers for indirect address-
ing. These registers are:
• INDF0 and FSR0
• INDF1 and FSR1
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers activates
indirect addressing, with the value in the correspond-
ing FSR register being the address of the data. The
FSR is an 8-bit register and allows addressing any-
where in the 256-byte data memory address range.
For banked memory, the bank of memory accessed is
specified by the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
6.4.2
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two con-
trol bits associated with each FSR register. These two
bits configure the FSR register to:
• Auto-decrement the value (address) in the FSR
• Auto-increment the value (address) in the FSR
• No change to the value (address) in the FSR after
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPF and MOVFP instructions, where either
'p' or 'f' is specified as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
DS30412C-page 40
after an indirect access
after an indirect access
an indirect access
INDIRECT ADDRESSING REGISTERS
INDIRECT ADDRESSING OPERATION
A simple program to clear RAM from 20h - FFh is
shown in Example 6-1.
EXAMPLE 6-1:
LP
6.5
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWT and
TABLRD.
The TABLRD and the TABLWT instructions allow trans-
fer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
6.6
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or pro-
gram memory. The table latch is used as a temporary
holding latch during data transfer between program and
data memory (see descriptions of instructions TABLRD,
TABLWT, TLRD and TLWT). For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
CLRF
CPFSEQ
GOTO
:
:
Table Pointer (TBLPTRL and
TBLPTRH)
Table Latch (TBLATH, TBLATL)
0x20
FSR0
ALUSTA, FS1
ALUSTA, FS0
ALUSTA, C
END_RAM + 1
INDF0
FSR0
LP
INDIRECT ADDRESSING
1996 Microchip Technology Inc.
;
; FSR0 = 20h
; Increment FSR
; after access
; C = 0
;
; Addr(FSR) = 0
; FSR0 = END_RAM+1?
; NO, clear next
; YES, All RAM is
; cleared