PIC17C44-16/L Microchip Technology, PIC17C44-16/L Datasheet - Page 14
![IC MCU OTP 8KX16 PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC17C44-16/L
Manufacturer Part Number
PIC17C44-16/L
Description
IC MCU OTP 8KX16 PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C44-16L.pdf
(4 pages)
Specifications of PIC17C44-16/L
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
16MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Controller Family/series
PIC17
No. Of I/o's
33
Ram Memory Size
454Byte
Cpu Speed
16MHz
No. Of Timers
4
No. Of Pwm Channels
2
Embedded Interface Type
USART
Rohs Compliant
Yes
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
454 B
Interface Type
SCI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C44-16/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 3-3.
FIGURE 3-3:
EXAMPLE 3-2:
DS30412C-page 14
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(RC mode)
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
Tcy0
PC
Q3
Q4
Execute 1
Fetch 2
Tcy1
Q1
Execute INST (PC)
Fetch INST (PC+1)
Q2
Execute 2
Fetch 3
PC+1
Tcy2
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO ) then
two cycles are required to complete the instruction
(Example 3-2).
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
Tcy3
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
Tcy4
PC+2
1996 Microchip Technology Inc.
Q3
Q4
Tcy5
Internal
phase
clock
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