PIC18F4685-I/ML Microchip Technology, PIC18F4685-I/ML Datasheet - Page 39

• Manufacturer Part Number: PIC18F4685-I/ML
• Description: IC PIC MCU FLASH 48KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4685-I/ML

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

3.3
The power-managed Sleep mode in the PIC18F2682/
2685/4682/4685 devices is identical to the legacy
Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by
interrupt, Reset or WDT time-out), the device will not
be clocked until the clock source selected by the
SCS1:SCS0 bits becomes ready (see Figure 3-6), or
it will be clocked from the internal oscillator block if
either the Two-Speed Start-up or the Fail-Safe Clock
Monitor are enabled (see Section 24.0 “Special
Features of the CPU”). In either case, the OSTS bit
is set when the primary clock is providing the device
clocks. The IDLEN and SCS bits are not affected by
the wake-up.
FIGURE 3-5:
FIGURE 3-6:
© 2009 Microchip Technology Inc.
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
Note1: T
CPU Clock
PLL Clock
Peripheral
Sleep Mode
Program
Counter
Output
Q1
OSC1
Clock
OST
Q2
PC
= 1024 T
Q3
Wake Event
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
OSC
Q1
; T
Q1
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
T
PLL
OSTS bit Set
PIC18F2682/2685/4682/4685
(1)
Q2 Q3 Q4 Q1 Q2
3.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(parameter 38, Table 27-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT time-
out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
PC + 2
PC + 2
Q3 Q4 Q1 Q2
Idle Modes
PC + 4
Q3 Q4
Q1 Q2 Q3 Q4
PC + 6
DS39761C-page 39
CSD