PIC18F4685-I/ML Microchip Technology, PIC18F4685-I/ML Datasheet - Page 217

• Manufacturer Part Number: PIC18F4685-I/ML
• Description: IC PIC MCU FLASH 48KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4685-I/ML

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

17.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (T
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (T
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 17-19:
© 2009 Microchip Technology Inc.
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDA
SCL
BRG
), the SEN bit
BRG
), the SDA
PIC18F2682/2685/4682/4685
SDA = 1,
SCL = 1
T
BRG
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
Note:
Write to SSPBUF occurs here
T
BRG
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
2
1st bit
C module is reset into its Idle state.
WCOL Status Flag
T
BRG
2nd bit
DS39761C-page 217