PIC18F6621-I/PT Microchip Technology, PIC18F6621-I/PT Datasheet - Page 17

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details

3.3
Data EEPROM is accessed one byte at a time via an
address pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by load-
ing EEADR:EEADRH with the desired memory loca-
tion, EEDATA with the data to be written, and initiating
a memory write by appropriately configuring the
EECON1 and EECON2 registers. A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh immediately prior to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must still be held low for the time specified by parame-
ter P10 to allow high voltage discharge of the memory
array.
FIGURE 3-8:
 2003 Microchip Technology Inc.
PGC
PGD
Poll WR bit
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
PGD
PGC
4
0
DATA EEPROM WRITE TIMING
P5
BSF EECON1, WR
1
4-bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
PGD = Input
PGD = Input
15 16
P5A
4-bit Command
1
0
Poll WR bit, Repeat Until Clear
FIGURE 3-7:
2
0
3
0
P11A
(see below)
PIC18F6X2X/8X2X
4
0
P5
MOVWF TABLAT
1
No
2
Unlock Sequence
15 16
55h - EECON2
AAh - EECON2
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
Set Data
WR bit
Clear?
Done
Start
Done
P5A
?
Yes
Yes
(see Figure 4-6)
PGD = Output
Shift Out Data
DS30499B-page 17
No
P10
16-bit Data
Payload
1
n
2
n