AT89C51AC2-RLTUM Atmel, AT89C51AC2-RLTUM Datasheet - Page 94

• Manufacturer Part Number: AT89C51AC2-RLTUM
• Description: IC 8051 MCU FLASH 32K 44VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51AC2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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A/T89C51AC2
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register. This register also contains a global disable bit
which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the
bit values and priority levels associated with each combination.
Table 68. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt but not by another
low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of the higher priority level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, see Table 69.
Table 69. Interrupt Priority Within level
external interrupt (INT0)
external interrupt (INT1)
PCA (CF or CCFn)
Interrupt Name
UART (RI or TI)
Timer 0 (TF0)
Timer 1 (TF1)
Timer 2 (TF2)
ADC (ADCI)
IPH.x
0
0
1
1
Interrupt Address Vector
IPL.x
0003h
000Bh
0013h
001Bh
0033h
0023h
002Bh
0043h
0
1
0
1
Interrupt Level Priority
Priority Number
3 (Highest)
0 (Lowest)
1
2
1
2
3
4
5
6
7
9
4127H–8051–02/08