AT89C51AC2-RLTUM Atmel, AT89C51AC2-RLTUM Datasheet - Page 91
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AT89C51AC2-RLTUM
Manufacturer Part Number
AT89C51AC2-RLTUM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51AC2-RLTUM.pdf
(121 pages)
Specifications of AT89C51AC2-RLTUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1280 B
Interface Type
UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Registers
4127H–8051–02/08
Table 63. ADCF Register
ADCF (S:F6h)
ADC Configuration
Reset Value = 0000 0000b
Table 64. ADCON Register
ADCON (S:F3h)
ADC Control Register
Reset Value = X000 0000b
Number
Number
CH 7
Bit
Bit
7-0
2-0
7
7
-
7
6
5
4
3
Mnemonic Description
Mnemonic Description
PSIDLE
PSIDLE
ADEOC
SCH2:0
ADSST
CH 0:7
ADEN
CH 6
Bit
Bit
6
6
-
Channel Configuration
Set to use P1.x as ADC input.
Clear to use P1.x as standart I/O port.
Pseudo Idle Mode (Best Precision)
Set to put in idle mode during conversion
Clear to convert without idle mode.
Enable/Standby Mode
Set to enable ADC
Clear for Standby mode (power dissipation 1 uW).
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
Start and Status
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion
Selection of Channel to Convert
see Table 62
ADEN
CH 5
5
5
ADEOC
CH 4
4
4
ADSST
CH 3
3
3
SCH2
CH 2
2
2
SCH1
CH 1
1
1
SCH0
CH 0
0
0
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