PIC16F877-20/L Microchip Technology, PIC16F877-20/L Datasheet - Page 44

• Manufacturer Part Number: PIC16F877-20/L
• Description: IC MCU FLASH 8KX14 EE 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F877-20/L

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 44-PLCC
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP/PSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.87 mm
• Length: 16.59 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 16.59 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87X
Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF is used to
determine when the memory write completes. This flag
must be cleared in software before setting the WR bit.
For EEPROM data memory, once the WREN bit and
the WR bit have been set, the desired memory address
in EEADR will be erased, followed by a write of the data
in EEDATA. This operation takes place in parallel with
the microcontroller continuing to execute normally.
When the write is complete, the EEIF flag bit will be set.
For program memory, once the WREN bit and the WR
bit have been set, the microcontroller will cease to exe-
REGISTER 4-1:
DS30292C-page 42
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER (ADDRESS 18Ch)
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
Unimplemented: Read as '0'
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
EEPGD
R/W-x
(any MCLR Reset or any WDT Reset during normal operation)
can only be set (not cleared) in software.)
cleared) in software.)
U-0
—
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
cute instructions. The desired memory location pointed
to by EEADRH:EEADR will be erased. Then, the data
value in EEDATH:EEDATA will be programmed. When
complete, the EEIF flag bit will be set and the microcon-
troller will continue to execute code.
The WRERR bit is used to indicate when the
PIC16F87X device has been reset during a write oper-
ation. WRERR should be cleared after Power-on
Reset. Thereafter, it should be checked on any other
RESET. The WRERR bit is set when a write operation
is interrupted by a MCLR Reset, or a WDT Time-out
Reset, during normal operation. In these situations, fol-
lowing a RESET, the user should check the WRERR bit
and rewrite the memory location, if set. The contents of
the data registers, address registers and EEPGD bit
are not affected by either MCLR Reset, or WDT Time-
out Reset, during normal operation.
WRERR
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-x
WREN
R/W-0
2001 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0