PIC17C42A-25/P Microchip Technology, PIC17C42A-25/P Datasheet - Page 125
![IC MCU OTP 2KX16 PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC17C42A-25/P
Manufacturer Part Number
PIC17C42A-25/P
Description
IC MCU OTP 2KX16 PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C42A-16P.pdf
(4 pages)
Specifications of PIC17C42A-25/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
4KB (2K x 16)
Program Memory Type
OTP
Ram Size
232 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
232 B
Interface Type
SCI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
For Use With
DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC17C42A-25/P
Manufacturer:
MICROCLOCK
Quantity:
20 000
Company:
Part Number:
PIC17C42A-25/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC17C42A-25/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
1996 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register 'f'
Inclusive OR WREG with f
[ label ]
0
d
(WREG) .OR. (f)
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in regis-
ter 'f'.
1
1
IORWF
Z
Read
0000
Q2
0x13
0x91
0x13
0x93
f
[0,1]
255
RESULT, 0
IORWF
100d
Execute
Q3
f,d
ffff
(dest)
destination
Write to
Q4
ffff
LCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
SUBROUTINE =
PC
PC
Q1
Long Call
[ label ]
0
PC + 1
k
None
LCALL allows an unconditional subrou-
tine call to anywhere within the 64k pro-
gram memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
1
2
MOVLW
MOVPF
LCALL
literal 'k'
Read
NOP
1011
Q2
=
=
k
PCL, (PCLATH)
255
16-bit Address
?
Address (SUBROUTINE)
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
PIC17C4X
LCALL
TOS;
0111
Execute
Execute
Q3
DS30412C-page 125
k
kkkk
register PCL
PCH
Write
NOP
Q4
kkkk
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