DSPIC30F5013-20I/PT Microchip Technology, DSPIC30F5013-20I/PT Datasheet - Page 122

• Manufacturer Part Number: DSPIC30F5013-20I/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501320IPT

dsPIC30F5011/5013
18.3.6
When the DCI module is operating as a frame sync
slave (COFSD = 1), data transfers are controlled by the
codec device attached to the DCI module. The COFSM
control bits control how the DCI module responds to
incoming COFS signals.
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is
sampled high (see Figure 18-2). The pulse on the
COFS pin resets the frame sync generator logic.
FIGURE 18-2:
FIGURE 18-3:
FIGURE 18-4:
DS70116H-page 122
Note:
SLAVE FRAME SYNC OPERATION
CSDO or CSDI
CSDI or CSDO
CSDI/CSDO
A 5-bit transfer is shown here for illustration purposes. The I
will be system dependent.
BIT_CLK
CSCK
COFS
SYNC
CSCK
FRAME SYNC TIMING, MULTI-CHANNEL MODE
FRAME SYNC TIMING, AC-LINK START-OF-FRAME
I
2
S INTERFACE FRAME SYNC TIMING
WS
MSB
bit 2
S12
MSB
bit 1
S12
S12
LSb
MSb
Tag
bit 14
In the I
one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or
falling edge on the COFS pin resets the frame sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operating in the Slave mode. Once a valid frame sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer will take place. The
module will not respond to further frame sync pulses
until the data frame transfer has completed.
Tag
LSB MSB
bit 13
Tag
2
2
S protocol does not specify word length – this
S mode, a new data word will be transferred
LSB
© 2008 Microchip Technology Inc.
LSB