DSPIC33FJ64GS610-I/PT Microchip Technology, DSPIC33FJ64GS610-I/PT Datasheet - Page 237
![IC MCU/DSP 64KB FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64GS610-I/PT
Manufacturer Part Number
DSPIC33FJ64GS610-I/PT
Description
IC MCU/DSP 64KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64GS610-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
85
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
85
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
On-chip Dac
10 bit, 4 Channel
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER
2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
FLTSTAT
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
HS/HC-0
R/W-0
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
3: These bits should not be changed after the PWM is enabled (PTEN = 1) (PTCON<15>).
4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
5: Center-Aligned mode ignores the least significant 3 bits of the duty cycle, phase, and dead time registers.
6: Configure CLMOD = 0 (FCLCONX<8>) and ITB = 1 (PWMCONx<9>) to operate in External Period Reset
DTC<1:0>
(1)
CAM bit is ignored.
The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest
clock.
mode.
FLTSTAT: Fault Interrupt Status bit
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit
1 = PHASEx/SPHASEx registers provide time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
CLSTAT
HS/HC-0
R/W-0
(1)
HC = Cleared in Hardware HS = Set in Hardware
W = Writable bit
‘1’ = Bit is set
TRGSTAT
HS/HC-0
DTCP
R/W-0
(4)
FLTIEN
R/W-0
U-0
Preliminary
—
(1)
(3)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CLIEN
R/W-0
R/W-0
MTBS
CAM
TRGIEN
R/W-0
R/W-0
(2,3,5)
x = Bit is unknown
XPRES
R/W-0
R/W-0
ITB
(3)
(6)
DS70591C-page 237
MDCS
R/W-0
R/W-0
IUE
(3)
bit 8
bit 0
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