DSPIC33FJ128GP710-I/PT Microchip Technology, DSPIC33FJ128GP710-I/PT Datasheet - Page 5
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DSPIC33FJ128GP710-I/PT
Manufacturer Part Number
DSPIC33FJ128GP710-I/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
4.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ128GP710-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP710-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
ECAN
UART
ADC
DCI
SPI
SPI
I
I/O
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Transmission
Consumption
Sleep Mode
Generation
SDO1 Pin
Operation
Character
FRMDLY
Transmit
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
Current
Break
Slave
Mode
Data
—
Number
Item
54.
55.
56.
57.
58.
59.
60.
61.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
After the ACKSTAT bit is set when receiving a NACK, it may
be cleared by the reception of a Start or Stop bit.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause the SPI module to ignore written data.
When using more than one transmit buffer, the DCI module
will corrupt the data transmitted on the CSDO line.
The UART module will not generate back-to-back Break
characters.
The SDO1 pin may toggle while the device is being
programmed via PGECx/PGEDx pin pairs.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set to
‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
Issue Summary
PD
) of the
DS80446D-page 5
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X